Power conservation is becoming increasingly important to computer platforms, whether to save battery life for mobile platforms or to meet new energy conservation standards. In order to conserve power, processors or other components of the computing platform may enter a reduced power level after a defined period of inactivity. The processors may implement various levels of reduced power consumption (known as core states or C-states) with each successive level (higher C-states) further reducing the power and being entered after additional periods of inactivity. After extended periods of inactivity a processor may enter a reduced power level (mode) where a voltage rail (Vcc) is turned off or drops below a retention level so that logic on the computing platform connected to the voltage rail is turned off (e.g., deep power down, C6). When exiting the deep power down state, the Vcc is reapplied and the logic restores the values contained therein prior to entering the deep power down mode.